//=============================================================================
//		DP8051 SFRs
//=============================================================================
#ifndef __REGISTERS_H__
#define __REGISTERS_H__

//===========================================
//				BYTE Registers
//===========================================
sfr P0    = 0x80;
sfr SP    = 0x81;
sfr DPL   = 0x82;
sfr DPH   = 0x83;
sfr PCON  = 0x87;
sfr TCON  = 0x88;
sfr TMOD  = 0x89;
sfr TL0   = 0x8A;
sfr TL1   = 0x8B;
sfr TH0   = 0x8C;
sfr TH1   = 0x8D;
sfr CKCON = 0x8E;		//*** New in DP8051
sfr P1    = 0x90;
sfr EXIF  = 0x91;		//*** New in DP8051
sfr SCON  = 0x98;
sfr SBUF  = 0x99;
sfr TWBASE= 0x9a;		//*** TW88xx base address
sfr P2    = 0xA0;
sfr IE    = 0xA8;
sfr P3    = 0xB0;
sfr IP    = 0xB8;
sfr SCON1 = 0xC0;
sfr SBUF1 = 0xC1;
sfr T2CON = 0xC8;
sfr RCAP2L= 0xCA;
sfr RCAP2H= 0xCB;
sfr TL2   = 0xCC;		
sfr TH2   = 0xCD;
sfr PSW   = 0xD0;
sfr WDCON = 0xD8;		//*** New in DP8051
sfr ACC   = 0xE0;
sfr EIE   = 0xE8;		//*** New in DP8051
sfr TA    = 0xEB;		//*** New in DP8051
sfr B     = 0xF0;
sfr EIP	  = 0xF8;		//*** New in DP8051

#ifdef DP80390
sfr	UART0FIFO = 0x9E;
sfr	UART1FIFO = 0x9F;
#endif

sfr	CHPCON = 0xBF;
sfr	SFRAL  = 0xC4;
sfr	SFRAH  = 0xC5;
sfr	SFRFD  = 0xC6;
sfr	SFRCN  = 0xC7;
sfr	CHPENR = 0xF6;


//--- TW88 Core Extension
sfr	BANKREG 	= 0x9A;

#ifdef DP80390
sfr ESP		 = 0x9B;
sfr ACON	 = 0x9D;
sfr MCON  	 = 0xC6;		// 24bit RAM access DP80390
sfr DPX1   = 0x95;
sfr	MXAX	= 0xEA;		// DP80390
#else
sfr	SPICONTROL 	= 0x9B;
sfr	T0HIGH 		= 0x9C;
sfr	T0LOW 		= 0x9D;
sfr	T1HIGH 		= 0x9E;
sfr	T1LOW 		= 0x9F;
sfr	T2HIGH 		= 0x95;
sfr	T2LOW 		= 0x96;
sfr CACHE		= 0xE2;
#endif

sfr INTFLAG		= 0xFA;
sfr INTENABLE	= 0xFB;
sfr INTPRIORITY	= 0xFC;
sfr INTEDGE		= 0xFD;
sfr INTPOL		= 0xFE;

//===========================================
//				BIT Registers
//===========================================

//--- P0
sbit P0_0  = 0x80;
sbit P0_1  = 0x81;
sbit P0_2  = 0x82;
sbit P0_3  = 0x83;
sbit P0_4  = 0x84;
sbit P0_5  = 0x85;
sbit P0_6  = 0x86;
sbit P0_7  = 0x87;

//--- TCON
sbit IT0   = 0x88;
sbit IE0   = 0x89;
sbit IT1   = 0x8A;
sbit IE1   = 0x8B;
sbit TR0   = 0x8C;
sbit TF0   = 0x8D;
sbit TR1   = 0x8E;
sbit TF1   = 0x8F;

//--- P1
sbit P1_0  = 0x90;
sbit P1_1  = 0x91;
sbit P1_2  = 0x92;
sbit P1_3  = 0x93;
sbit P1_4  = 0x94;
sbit P1_5  = 0x95;
sbit P1_6  = 0x96;
sbit P1_7  = 0x97;

//--- (P1)
sbit T2    = 0x90;
sbit T2EX  = 0x91;

//--- SCON
sbit RI    = 0x98;
sbit TI    = 0x99;
sbit RB8   = 0x9A;
sbit TB8   = 0x9B;
sbit REN   = 0x9C;
sbit SM2   = 0x9D;
sbit SM1   = 0x9E;
sbit SM0   = 0x9F;

//--- SCON1
sbit RI1   = 0xc0;
sbit TI1   = 0xc1;
sbit RB18  = 0xc2;
sbit TB18  = 0xc3;
sbit REN1  = 0xc4;
sbit SM12  = 0xc5;
sbit SM11  = 0xc6;
sbit SM10  = 0xc7;

//--- P2
sbit P2_0  = 0xA0;
sbit P2_1  = 0xA1;
sbit P2_2  = 0xA2;
sbit P2_3  = 0xA3;
sbit P2_4  = 0xA4;
sbit P2_5  = 0xA5;
sbit P2_6  = 0xA6;
sbit P2_7  = 0xA7;

//--- IE
sbit EA    = 0xAF;
sbit ES1   = 0xAE;
sbit ET2   = 0xAD;
sbit ES    = 0xAC;
sbit ET1   = 0xAB;
sbit EX1   = 0xAA;
sbit ET0   = 0xA9;
sbit EX0   = 0xA8;

//--- P3
sbit P3_0  = 0xB0;
sbit P3_1  = 0xB1;
sbit P3_2  = 0xB2;
sbit P3_3  = 0xB3;
sbit P3_4  = 0xB4;
sbit P3_5  = 0xB5;
sbit P3_6  = 0xB6;
sbit P3_7  = 0xB7;

//--- (P3)
sbit RXD   = 0xB0;
sbit TXD   = 0xB1;
sbit INT0  = 0xB2;
sbit INT1  = 0xB3;
sbit T0    = 0xB4;
sbit T1    = 0xB5;
sbit WR    = 0xB6;
sbit RD    = 0xB7;

//--- IP
sbit PX0   = 0xB8;
sbit PT0   = 0xB9;
sbit PX1   = 0xBA;
sbit PT1   = 0xBB;
sbit PS    = 0xBC;
sbit PT2   = 0xBD;
sbit PS1   = 0xBE;

//--- T2CON
sbit CP_RL2= 0xC8;
sbit C_T2  = 0xC9;
sbit TR2   = 0xCA;
sbit EXEN2 = 0xCB;
sbit TCLK  = 0xCC;
sbit RCLK  = 0xCD;
sbit EXF2  = 0xCE;
sbit TF2   = 0xCF;

//--- PSW
sbit P     = 0xD0;
sbit OV    = 0xD2;
sbit RS0   = 0xD3;
sbit RS1   = 0xD4;
sbit F0    = 0xD5;
sbit AC    = 0xD6;
sbit CY    = 0xD7;

//--- WDCON
sbit RWT   = 0xd8;		// Run Watchdog Timer
sbit EWT   = 0xd9;		// Enable Watchdog Timer
sbit WTRF  = 0xda;		// Watchdog Timer Reset Flag
sbit WDIF  = 0xdb;		// Watchdog Interrupt Flag

//--- EIE 
sbit EINT2 = 0xe8;		// Enable Ex.Int 2
sbit EINT3 = 0xe9;		// Enable Ex.Int 3
sbit EINT4 = 0xea;		// Enable Ex.Int 4
sbit EINT5 = 0xeb;		// Enable Ex.Int 5
sbit EINT6 = 0xec;		// Enable Ex.Int 6
sbit EWDI  = 0xed;		// Enable WatchDog Int

//--- EIP
sbit PINT2 = 0xf8;		// Priority Ex.Int 2
sbit PINT3 = 0xf9;		// Priority Ex.Int 3
sbit PINT4 = 0xfa;		// Priority Ex.Int 4
sbit PINT5 = 0xfb;		// Priority Ex.Int 5
sbit PINT6 = 0xfc;		// Priority Ex.Int 6
sbit PWDI  = 0xfd;		// Priority Watchdog Int

#endif  //__REGISTERS_H__











